Birbla

Join the discussion

Write your take first — we'll ask for email only when you're ready to publish.

Sign in
  • Hacker News
  • How does PIO compare to Cypress PSoC?
    by brcmthrowaway
  • This would be a great starting point to make a USB Ethernet NIC if someone were inclined to do it.

    It could even have a very practical use if it were made to impersonate a USB Ethernet device that the Nintendo Switch / Nintendo Switch 2 supports. They only support gigabit NICs, but it should be easy to just pretend that the other side failed to negotiate gigabit and only supports 100Mbps.

    by ryao
  • Would this have been possible without PIO?
    by unixfg
  • This is only talking about TX, presumably it can't receive? That'd be the hard part...
    by eqvinox
  • Something related to this that is really cool is directly reading from PDM microphones using PIO: https://github.com/ArmDeveloperEcosystem/microphone-library-.... This shouldn't be called bit-banging though if it's using PIO.
    by lukeinator42
  • Great hack from very talented hacker. Steve Markgraf is the author of High Speed Data Acquisition over HDMI https://github.com/steve-m/hsdaoh Capturing raw data using super cheap USB3 HDMI Video Capture dongles. Up to 175MB/s with Pico2 as the sender https://github.com/steve-m/hsdaoh-rp2350

    Sadly 100Mbit might be the limit for bitbanging ethernet. While 1Gbit uses easily reachable 125MHz clock it also does full duplex requiring echo cancellation and I dont see an easy way around external PHY. The next PICO challenge is implementing GRMII PHY support for that sweet $1 RTL8211 1Gbit. I havent seen that done yet.

    by rasz
  • Fun stuff. You kids don't know how lucky you are to have really capable MCU's for just a few bucks. :-)

    It is kind of the ultimate "not a TOE[1]" example yet.

    [1] TOE or TCP Offload Engine was a dedicated peripheral card that implements both the layer 1 (MAC), layer 2 (Ethernet), and layer 3 (IP) functions as a co-processing element to relieve the 'main' CPU the burden of doing all that.

    by ChuckMcM
  • this is classic computing wheel of life stuff (Bell, Mudge, MacNamara wrote that up in the 70s)

    * first you do it in the cpu * then you do it in a dedicated card off the bus * then you find the FPGA or whatever too slow, so you make the card have it's own CPU * then you wind up recursing over the problem, implementing some logic in a special area of the cpu, to optimise its bus to the other bus to ...

    I expect to come back in 10years and find there is a chiplet which took the rpi core, and implements a shrunk version which can be reprogrammed, into the chiplet on the offload card, so we can program terabit network drivers with a general purpose CPU model.

    by ggm

Explore Birbla archives