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  • Hacker News
  • when I designed my own simple risc-v processor with just rv32i, i just compiled lua. Hassle free
  • We got RISC-V support before an official 3.14t docker image.
  • For quite some times I'm wondering how I could invest in RISC, or RISC related manufacturer but it looks like all companies are private.
  • Did they already test how the proposed jit fares on RISC-V?
    by Qem
  • Odd they still have i686-pc-windows-msvc as Tier 1 *. Even Microsoft doesn't have any supported 32bit Windows versions anymore, and C extension modules likely follow Linux (where Python doesn't have any no supported i686 triplets in any tier). It would be more modern to demote its Tier and promote aarch64 Windows or wasm32 instead to Tier 1.

    * https://peps.python.org/pep-0011/#tier-1

    by yyyk
  • > RISC-V is now officially supported by CPython as a tier 3 platform!

    That's significant, but tier 3 is still a caveat. Still allowed to break without blocking anything or being fixed as a priority.

  • CPython is written in C, did running it on Risc-V take more than a recompilation? Were there any surprises? Yes of course it needs testing and RISC-V in the CI stack, but I'd expect fairly smooth sailing.
  • What RISC-V extensions is this built for? There is a target triple of riscv64-unknown-linux-gnu listed so i assume the baseline RV64GC that the Linux kernel is built against.

    It makes sense to be conservative with a new architecture but new high performance RISC-V cores such as from SiFive[1] are going to meet RVA23. That standard has vector and bit manipulation extensions that could be used to improve performance with a python interpreter. I guess more testing needs to be done to see if raising the bar is useful.

    [1]https://www.sifive.com/cores/performance-p800

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