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- Hacker News
- hand weaving thousands of tiny cores is the part i cant get over. my dad had a bead loom kit for making belts and i could never keep the pattern straight, gave up after twenty rows or so. were boards like this still assembled by hand in 1980, or did they have machines doing it by then?
- Space. Space. Wanna go to space.by liminal-dev
- Built by highly skilled humans.by annoyingnoob
- I saw this in person and then again on Dr Stoneby galvanust
- Funny to see that frontpage as earlier on today I made a comment saying that with LLMs I'm betting we'll see N-modular redundancy systems soon, with a ultra-hardened, minimal, part picking the majority votes of N LLM-written implementations (in different languages, on different stacks, all running at the same time). Not 100% TFA but "computing in space" involved a lot of N-modular redundancy systems.
The reason I'm 99.9% sure we'll see that is that it'll help catch both bugs in the LLMs implementations themselves (and we know there are plenty of those) but also in the stacks/platforms/VMs running those software.
Imagine one spec and five implementations (Rust, Go, Java, Python, whatever) and one minimal system, with the tiniest of the tiniest attack surface, returning the answer as soon as 3-of-5 agree. And, as a bonus, if later on one the two "missing" answer arrives and doesn't match, it's cause for enquiry and bugs be smashed.
Basically (and although I don't care about Ethereum or cryptocurrencies except for the cryptographic aspect), we already witnessed that: 3 different implementations of Ethereum and, in the early days, one of the implementation whose result differed from the two others. And hence the implementation not respecting the spec (in that case it was the only one that was faulty) got instantly detected (and promptly patched). My memory is fuzzy but I know this happened.
Heck, I may write a proof-of-concept for fun.
I've got other ideas as to what will be possible in the future but I'm keeping them for another day.
- This all rests on the assumption that design errors are independent beween LLM-generated programs for the same specification. That's not true for humans (Knight and Leveson, 1986) and I highly doubt it's any more true for robots.
(On the other hand I just found out about Ron, Baudry, Monperrus, 2026, which seems to say "sure, problems are correlated, but it could still be useful.")
by kqr - The architecture without inhibit lines is interesting. Did this make the memory faster, or was the main goal simply to reduce the number of sense amplifiers and simplify the board layout?by imnotr0b0t
- The main reason was the "inhibit recovery problem". The inhibit line required a large current that went through all the cores. This caused electrical noise, requiring a delay while the noise settled down. Doing away with the inhibit line thus helped performance. The drive lines are also shorter, which also helps performance.
The paper "2 1/2 D High Speed Memory Systems: Past, Present, and Future" explains this, but not entirely clearly: https://ieeexplore.ieee.org/document/4038821
by kens - Amazing how reliable core memory was for critical systems, even in space. Bet it weighed a ton compared to modern RAM.by lampcord
- It's one of those technologies that makes you wonder what would've happened if they just kept advancing it instead of outright replacing it with something else entirely. How tiny could cores be made? Could modern chip manufacturing techniques be used to make nano-scale core memory?
See also: vacuum tubes (there were attempts to miniaturize them to try to compete with transistors), CRT displays (there were some wild concepts like a flat-panel CRT where the gun is at the top and the beam makes a 180° turn at the bottom before it gets deflected into the screen; also late CRT TVs that had slimmer tubes).
by grishka - Author here for all your core memory questions...by kens
- Can I confess I've never quite wrapped my head around the application of the 'inhibit' line in this?
If a write cycle is just a read cycle with a) a reversed polarity and b) you don't care about the contents of the sense line - I don't get why current coincidence is sufficient during the read cycle, but not during the write cycle?
Every description of this I've ever read, sound like inhibit and current coincidence solve the same problem - but have never left me clear on why we need to solve it twice.
by soneil - No special provisions for rad hardening needed?by Zigurd
- Please write an article about that French computer Project idea: find 64kb kb of such memory and connect it somehow into Apple2, atari and other 8bit cpus hehe
It must be possible to have some hardware adapter to map RAM into that type of memory.
Or even over serial...
ps. Related story: around 10 years ago Texas Instruments started to use FRAM in some of their 16 bit MCUs (msp430 family)
It works exactly like core memory - data still intact after power resets.
by iberator